The present invention generally relates to integrated circuits, and more particularly to apparatus and methods for boosting CAM gate voltages in reading a CAM cell.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical data cell stores a single piece of binary information referred to as a bit having one of two possible states. The memory data cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual data cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the data cells within a specific byte or word. The individual memory cells typically comprise a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
In addition to data storage cells, other peripheral information related to the memory device may be stored in one or more content addressable memory (CAM) devices. For instance, CAM devices may be provided in a memory device for storing information relating to write protection, redundancy, addressing, and/or decoding, wherein such information may be used internally for various operations. In this regard, the CAM devices may be configured as individual cells for storing one or more bits of such information, and/or in CAM arrays. In one example, a CAM cell may be used to indicate that a sector of data memory cells is defective, whereby a redundancy scheme within the memory device may alternatively employ a redundant sector for storage and retrieval of user data. Another exemplary usage of a CAM device involves storing a bit in a CAM cell indicating whether or not such redundancy is enabled.
Like the data memory cells, CAM cells are comprised of semiconductor devices, such as MOS transistors having gate, drain, and source terminals. The programming, erasing, and reading of such CAM cells are commonly performed by application of appropriate voltages to certain terminals of the CAM cell MOS device. In a CAM erase or program operation, the voltages are applied so as to cause a charge to be stored in or removed from the memory cell. In reading the CAM cell, appropriate voltages are applied so as to cause a current to flow in the CAM cell, wherein the amount of such CAM cell current is indicative of the value of the data stored therein. The associated CAM read circuitry includes appropriate circuitry to sense the resulting CAM cell current in order to determine the data stored therein.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 1MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, the data cells and CAM cells typically include a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
Such a single bit stacked gate flash memory CAM cell is programmed by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the CAM cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the CAM cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory CAM cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a conventional CAM read operation, a certain voltage bias is applied across the drain and source of the cell transistor. The voltage at the drain in conventional stacked gate CAM cells is typically provided at between about 0.5 and 1.0 volts in a read operation. A voltage between approximately 0.5 and 2.0 volts is then applied to the CAM cell gate terminal in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed cell threshold voltage (VT) and an unprogrammed cell threshold voltage, wherein the erased cell threshold voltage is approximately 0.5 volts and the programmed cell threshold voltage is around 2.0 volts. The resulting current is measured, by which a determination is made as to the data value stored in the CAM cell.
More recently, dual bit CAM cells have been introduced, which allow the storage of one or two bits of information in a single memory CAM cell. However, the gate voltage required to read dual bit CAM cells is typically higher than that of single bit, stacked gate architecture CAM cells, due to the physical construction of the dual bit cell. For example, some dual bit memory cell architectures require between about 2.0 and 3.5 volts at the CAM cell gate terminal in order to properly read the CAM contents. Conventional CAM read circuitry for single bit stacked gate CAM cells provide the gate voltage using a voltage divider circuit associated with a supply voltage (e.g., VCC). Because the voltage applied to the gate of such conventional CAM cells is derived from the memory device supply voltage, however, the ability to provide the higher gate voltage required to read the newer dual bit CAM cells may be impaired when the supply voltage is at or near lower rated levels (e.g., 2.7 to 3.6 volts). In addition, low power applications for memory devices, such as cellular telephones, laptop computers, and the like, may further reduce the supply voltage available.
Accordingly, there is a need for improved memory devices and CAM read circuitry which allow proper reading of dual bit architecture CAM cells, and which operate at reduced supply voltages.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention provides a memory device with a CAM cell and a read circuit for reading the CAM cell using a boosted CAM gate voltage. The invention finds application in association with a variety of CAM cell read techniques, including the ratio method, wherein the ratio of current through the CAM cell is compared with that of a reference transistor. Also disclosed is a method for reading a memory device CAM cell, wherein a boosted voltage is provided to the CAM cell gate.
According to one aspect of the present invention, there is provided a memory device having a CAM cell and a voltage booster providing a boosted voltage to the CAM gate during a CAM read operation. The booster provides a gate voltage independent of variations in the supply voltage, whereby reliable CAM read operation may be realized. The CAM cell may be used to indicate one or more binary values associated with conditions in the memory device, such as a redundancy enable status, write protection, and the like. The voltage booster is connected between the gate terminal of the CAM cell and a supply voltage, and provides a boosted voltage to the gate terminal of the CAM cell during the CAM read operation, wherein the boosted voltage is greater than an erased CAM cell threshold voltage and less than a programmed CAM cell threshold voltage.
Another aspect of the invention provides a method of reading a CAM cell associated with a memory device. The methodology comprises providing a drain read voltage to a drain terminal of the CAM cell, providing a source voltage to a source terminal of the CAM cell, and providing a boosted voltage to a gate terminal of the CAM cell. The resulting CAM cell current may then be measured in order to determine the data stored in the CAM cell.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.